A logic state is stored in a cell by programming its threshold voltage. In nonvolatile memory devices, this is done by transferring a certain electrical charge in a floating gate of the cell.
The storage capacity of memory devices can be multiplied by storing more than one bit of information in each single cell of the same physical structure as if it is intended to store a single information bit. This is in addition to increasing the integration density of arrays of cells individually addressable through wordlines and bitlines of the array.
Though based on the same physical mechanisms, the programming and reading of cells that store more than one bit (multi-level cells) are carried out with techniques that differ from those used for cells that store a single bit (two-level cells).
To read a two-level memory array cell, a certain voltage is applied to the control gate (wordline) of the cell. The value of a reading voltage is between the threshold voltage of an erased cell and the threshold voltage of a programmed cell such that when the cell is programmed, the reading voltage is lower than its threshold voltage. As a consequence, no current flows through the cell. In contrast, when the cell is erased, the reading voltage is higher than its threshold voltage, and thus a current flows through the cell.
In four-level cells, two bits of information may be stored by making the programming voltages of the different thresholds that may be set for one memory cell define four different intervals. Each interval is associated to a respective two-bit datum. A reading operation is carried out by comparing an electrical parameter, correlated with the current that flows through the cell, with four distinct reference intervals. The intervals are defined by the three different thresholds that may be programmed for each single cell. Each cell is associated with a respective two-bit datum, and thus determining the logic datum associated to the distinct interval of values (threshold voltage distributions) in which the measured electrical parameter falls. This approach for a multi-level operation of the cells is applicable to volatile memory cells, such as DRAMs, as well as to nonvolatile memory devices, such as EEPROMs and FLASH-EPROMs.
A basic circuit scheme of two memory array bitlines and a page buffer of a four-level memory of the FLASH type is depicted in FIG. 1. The page buffer manages the operations of reading the information stored in the memory cells of a selected memory page, or writing new information in the cells. The selection transistors MDSL and MSSL connect to the bitline or to ground, respectively, the series of memory cells.
The basic operations that usually are performed on the memory cells are a page read (an operation involving reading data from a selected memory page), a page program (writing data into a selected memory page), and an erase operation (the content of the memory cells is erased).
In four-level memory devices, a two-bits datum may be stored in each cell by programming the latter in any one of four different states. Each one is associated with a corresponding logic value of the two-bits datum. Usually, the programming state of a memory cell is defined by the threshold voltage value of the transistor structure that is included in the memory cell structure.
In a memory cell adapted to store two bits, the threshold voltage values of the memory cells may assume one of four different values or ranges of values. A typical choice is to associate the logic values of the stored bit pair to the four different states according to a binary sequence 11, 10, 01, and 00, as shown in FIG. 2, corresponding to increasing threshold voltage values, with the logic value 11 that is associated with the state of the lowest threshold voltage value (erased state). The others are associated in succession to states of increased threshold voltage values.
The cells of a memory page (wordline), both if they are intended to store one bit or two bits of information, are programmed in parallel by incrementing stepwise their threshold voltage. Typically, the PAGE BUFFER biases the bitline at the ground potential for programming the cells, or to a supply potential VDD for not programming the cells. The control voltage DSL of the selection transistor MDSL of the series (stack) to which the wordline to be programmed belongs is at the supply voltage VDD. This is while the control signal SSL (source selector) is at the ground potential while the source line (not depicted) is at the voltage VDD.
A typical timing diagram of the main signals during the execution of the sequence of steps for programming a bitline BLE is depicted in FIG. 4. All the bitlines are charged (FIG. 3), and the gate of the selection transistors DSL are brought at the supply potential VDD. The channels are biased at the voltage VDD-VTH, where VTH is the threshold of the selection transistors MDSL.
Then the control signal SELBLE is asserted while the signals DISCHE, DISCHO are switched to turn off the respective transistors, and the page buffer discharges only the bitlines that contain cells that should be programmed. This is while leaving at the supply voltage VDD all the cells that should not be programmed, as shown in FIG. 5. After this phase, all the wordlines are biased at an intermediate voltage, typically about 8 to 10V. Then the wordlines to be programmed are biased from this intermediate voltage to the programming voltage.
This step may take place in two ways. One way is for the gate of the cell to be programmed to be directly brought to the programming voltage. But in this case, the resistance and the capacitance of the row determines the charge time. Alternatively, the programming voltage is attained in a controlled fashion by imposing a voltage ramp with a desired slope, for example a slope of 1 V/μs.
Because of the very small pitch of the cells, the coupling capacitances between the wordline and the line DSL (but also among the wordlines themselves) is relatively large. If the gate of the selected cell is biased directly at the programming voltage, the voltage on the line DSL could increase, especially when the cell adjacent to the transistor MDSL is to be programmed above the voltage VDD.
Since the unselected bitlines are biased at the voltage VDD, increasing the gate voltage of the transistor MDSL could reduce the bias voltage of the relative channel. Because of the capacitive coupling between the wordline and the line DSL, the gate voltage of the transistor MDSL could surpass the supply voltage VDD by at least a threshold voltage and the selection switch MDSL, could be turned on. This would connect the channel, at a boosted voltage, to the respective bitline that is at the supply voltage. As a consequence, the cells that are on the same wordline of a cell to be programmed could be programmed even if they should not be programmed.
To address this problem, the bitline is biased at a voltage larger than VDD. The drawbacks of this approach is that there is an increment of silicon area consumption because of the need of integrating additional charge pump generators capable of supplying a current and a voltage sufficient for inhibiting the cells not to be programmed. Also, the time required for biasing all the bitlines is increased.